1. Field of the Invention
This application claims of priority from Japanese Patent Appln. No. 2004-254852, filed Sep. 1, 2004, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a wired circuit board and, more particularly, to a wired circuit board used for electronics.
2. Description of the Prior Art
In general, a wired circuit board, such as a flexible wired circuit board, comprises an insulating base layer, a conductive pattern formed on the insulating base layer, and an insulating cover layer formed on the insulating base layer to cover the conductive pattern.
This general wired circuit board is required to improve adhesion of the conductive pattern to the insulating base layer to prevent stripping of the conductive pattern from the insulating base layer, for improvement in fine pitch of the conductive pattern.
For example, a technique has been proposed to ensure the adhesion of the circuit to the insulating layer by adhesively bonding a resin film consisting primarily of thermosetting resin to a substrate to form an insulating layer in the B stage state on the substrate, then forming the circuit on the insulating layer by plating, then embedding the circuit in the insulating layer under pressure, and finally curing the insulating layer completely to the C stage state (Cf. JP Laid-open (Unexamined) Patent Publication No. 2004-179341, for example).
In this wired circuit board, the conductive pattern is partly exposed from the insulating cover layer, and the exposed portion of the conductive pattern is formed as a connecting terminal portion for connecting to external terminals.
It is known that in order to improve the reliability of the connecting terminal portion connecting to the external terminals or prevent the corrosion, a metal plating layer, such as a nickel plating layer and a gold plating layer, is formed on a surface of the connecting terminal portion (Cf. JP Laid-open (Unexamined) Patent Publication No. 2002-185133, for example).
However, in this wired circuit board, there is the possibility when the metal plating layer is formed, a plating solution may infiltrate in an interface between the metal plating layer and the insulating base layer and remain therein, so that ionic impurities in the plating solution, such as chloride ion, may remain as a residual or ionic contamination. When electric current flows through the circuit under a high temperature and high humidity environment over a long term in the state of such a residual remaining, a short circuit may occur from ionic migration, then leading to insulating failure.
The method disclosed by JP Laid-open (Unexamined) Patent Publication No. 2004-179341 as cited above may provide improved adhesion between the insulating base layer and the conductive pattern, but suffers from difficulties in preventing occurrence of the short circuit from the ionic migration.